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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. august 2008 rev 4 1/81 1 STM8S20XXX performance line, 24 mhz. 8-bi t mcu, up to 128 kbytes flash, integrated eeprom,10-bit adc, timers, 2 uarts, spi, i2c, can features core max f cpu : up to 24 mhz, 0 wait states @ f cpu 16 mhz advanced stm8 core with harvard architecture and 3-stage pipeline extended instruction set max. 20 mips @ 24 mhz memories program memory: up to 128 kbytes flash; data retention 20 years at 55c after 10 kcycles data memory: up to 2 kbytes true data eeprom; endurance 300 kcycles ram: up to 6 kbytes clock, reset and supply management 3.0 to 5.5 v operating voltage flexible clock control, 4 master cl ock sources: ? low power crystal resonator oscillator ? external clock input ? internal, user-trimmable 16 mhz rc ? internal low power 128 khz rc clock security system with clock monitor power management: ? low power modes (wait, active-halt, halt) ? switch-off peripheral clocks individually permanently active, low consumption power- on and power-down reset interrupt management nested interrupt contro ller with 32 interrupts up to 37 external interrupts on 6 vectors timers 2x 16-bit general purpose timers, with 2+3 capcom channels (ic, oc or pwm) advanced control timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead-time insertion and flexible synchronization 8-bit basic timer with 8-bit prescaler auto wake-up timer window watchdog and independent watchdog communications interfaces high speed 1 mbit/s acti ve can 2.0b interface uart with clock output for synchronous operation - lin master mode uart with lin 2.1 compliant, master/slave modes and automatic resynchronization spi interface up to 10 mbit/s i 2 c interface up to 400 kbit/s analog to digital converter (adc) 10-bit, 1 lsb adc with up to 16 channels i/os up to 68 i/os on an 80-pin package including 11 high sink outputs highly robust i/o design, immune against current injection development support ? single wire interface module (swim) and debug module (dm) for fast on-chip programming and non-intrusive debugging table 1. device summary reference part number stm8s207xx stm8s207mb, stm8s207rb, stm8s207r8, st m8s207r6, stm8s207cb, stm8s207c8, stm8s207s8, stm8s207k6, stm8s207k4 stm8s208xx stm8s2 08mb, stm8s208rb lqfp80 14x14 lqfp48 7x7 lqfp64 10x10 lqfp44 10x10 or 14x14 lqfp32 7x7 vfqfn32 5x5 www.st.com
contents STM8S20XXX 2/81 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 single wire interface module (swim) and debug module (dm) . . . . . . . . 13 4.3 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 flash program and data eeprom memory . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 auto wake-up counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.10 tim1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.11 tim2, tim3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 17 4.12 tim4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.13 analog/digital converter (adc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.14 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.14.1 uart1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.14.2 uart3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14.3 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.4 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.5 can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM8S20XXX contents 3/81 7 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.1 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3.2 external clock sources and timing characteristics . . . . . . . . . . . . . . . . . 44 7.3.3 internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 46 7.3.4 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.3.5 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.3.6 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.3.7 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.3.8 spi serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.3.9 i2c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.3.10 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.4.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.4.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 68 8 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.1.1 lqfp package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.1.2 qfn package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9 stm8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.1 emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.2 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.2.1 stm8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.2.2 c and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
contents STM8S20XXX 4/81 10 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
STM8S20XXX list of tables 5/81 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. STM8S20XXX performance line features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. tim timer features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. legend/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6. option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 9. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 11. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 12. operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 13. total current consumption in run, wait and slow modes at v dd = 5.0 v. . . . . . . . . . . . . . . 39 table 14. total current consumption and ti ming in halt, fast active halt and slow active halt modes at v dd = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 15. total current consumption in run, wait and slow modes at v dd = 3.3 v. . . . . . . . . . . . . . . 40 table 16. total current consumption and ti ming in halt, fast active halt and slow active halt modes at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18. hse user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 table 19. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 20. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 21. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 22. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 23. flash program memory/data eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 24. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 25. output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 26. output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 27. output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 28. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 29. tim 1, 2, 3 characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 30. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 31. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 32. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 33. adc accuracy with r ain < 10 k r ain , v dda = 3.3 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 34. adc accuracy with r ain < 10 k , v dda = 5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 35. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 36. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 37. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 38. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 39. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 40. 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 41. 64-pin low profile quad flat package mechanical data (10 x 10) . . . . . . . . . . . . . . . . . . . . . 71 table 42. 64-pin low profile quad flat package mechanical data (14 x14) . . . . . . . . . . . . . . . . . . . . . 72 table 43. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 44. 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 45. 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 46. 32-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . . 76
list of tables STM8S20XXX 6/81 table 47. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
STM8S20XXX list of figures 7/81 list of figures figure 1. stm8s20x performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. lqfp 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4. lqfp 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5. lqfp 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. lqfp 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7. vqfn32/lqfp 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 9. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 10. f cpumax versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11. typ. idd(run)hse vs. vdd @ fcpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 12. typ. idd(run)hse vs. fcpu @ vdd = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 13. typ. idd(run)hsi vs. vdd @ fcpu = 16 mhz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 14. typ. idd(wfi)hse vs. vdd @ fcpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15. typ. idd(wfi)hse vs. fcpu @ vdd = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 16. typ. idd(wfi)hsi vs. vdd @ fcpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 17. hse external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 18. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 19. typical hsi frequency vs v dd @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 20. typical lsi frequency vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 21. typical v il and v ih vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 22. typical pull-up resistance r pu vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 23. typical pull-up current i pu vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 24. typ. vol @ vdd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 25. typ. vol @ vdd = 5.0 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 26. typ. vol @ vdd = 3.3 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 27. typ. vol @ vdd = 5.0 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 28. typ. vol @ vdd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 29. typ. vol @ vdd = 5.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 30. typ. vdd - voh @ vdd = 3.3 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 31. typ. vdd - voh @ vdd = 5.0 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 32. typ. vdd - voh @ vdd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 33. typ. vdd - voh @ vdd = 5.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 34. typical nrst v il and v ih vs v dd @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 35. typical nrst pull-up resistance r pu vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . 55 figure 36. typical nrst pull-up current i pu vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 55 figure 37. recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 38. spi timing diagram - slave mode and cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 39. spi timing diagram - slave mode and cpha=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 40. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 41. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 42. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 43. 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 44. 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 45. 64-pin low profile quad flat package (14 x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 46. 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 47. 44-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 48. 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
list of figures STM8S20XXX 8/81 figure 49. 32-lead very thin fine pitch quad flat no-lead package (5 x 5) . . . . . . . . . . . . . . . . . . . . . . 76 figure 50. stm8s207/208xx performance line ordering information scheme . . . . . . . . . . . . . . . . . . . 79
STM8S20XXX introduction 9/81 1 introduction this datasheet contains the description of the stm8s20x performance line features, pinout, electrical characteristics, mechanical data and ordering information. for complete information on the stm8s microcontroller memory, registers and peripherals, please refer to the stm8s microcontroller family reference manual (rm0016) for information on programming, erasing and protection of the internal flash memory please refer to the stm8s flash programming manual (pm0051) for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470) for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044)
description STM8S20XXX 10/81 2 description the stm8s20x performance line 8-bit microcontrollers offer 32 kbytes128 of program memory. all devices of the stm8s20x performance line provide the following benefits: reduced system cost ? high system integration level with intern al clock oscillators, watchdog and brown- out reset performance and robustness ? 20 mips at 24 mhz cpu clock frequency ? robust i/o, independent watchdogs with separate clock source ? clock security system short development cycles ? applications scalability across a comm on family product architecture with compatible pinout, memory map and and modular peripherals. ? full documentation and a wide choice of development tools product longevity ? advanced core and peripherals made in a state-of-the art technology ? a family of products for applications with 3.0 v to 5.5 v operating supply table 2. STM8S20XXX performance line features device pin count no. of maximum gpio (i/o) ext. interrupt pins timer capcom channels timer pwm channels (1) 1. including complementary outputs. a/d converter channels flash program memory (bytes) data eeprom (bytes) ram (bytes) becan interface stm8s207mb stm8s207r8 stm8s207r6 stm8s207rb stm8s207cb stm8s207c8 stm8s207s8 stm8s207k6 stm8s207k4 80 64 64 64 48 48 44 32 32 68 (2) 52 (2) 52 (2) 52 (2) 38 (3) 38 (3) 34 (3) 25 (3) 25 (3) 2. 11 high sink outputs (hs) 3. 9 high sink outputs (hs) 37 37 37 37 35 35 31 23 23 9 9 9 9 9 9 8 8 8 12 12 12 12 12 12 11 11 11 16 16 16 16 10 10 9 7 7 128k 64k 32k 128k 128k 64k 64k 32 16 2048 1536 1024 2048 2048 1536 1536 1024 1024 6k 4k 2k 6k 6k 4k 4k 2k 2k - stm8s208mb stm8s208rb 80 64 68 (2) 52 (2) 37 37 9 9 12 12 16 16 128k 128k 2048 2048 6k 6k ye s
STM8S20XXX block diagram 11/81 3 block diagram figure 1. stm8s20x performance line block diagram xtal 1-24 mhz rc int. 16 mhz rc int. 128 khz stm8 core debug/swim i 2 c spi uart1 uart3 awu timer reset block reset por bor clock controller detector clock to peripherals and core 10 mbit/s lin master 16 channels address and data bus window wdg up to 128 kbytes up to 2 kbytes up to 6 kbytes boot rom adc2 becan 9 capcom reset 400 kbit/s 1 mbit/s master/slave single wire autosynchro debug interf. spi emul. channels program flash data eeprom ram up to 16-bit general purpose 16-bit advanced control timer (tim1) timers (tim2, tim3) 8-bit basic timer (tim4) beeper 1/2/4 khz beep independent wdg
product overview STM8S20XXX 12/81 4 product overview the following section intends to give an overview of the basic features of the stm8s20x performance line functional modules and peripherals. for more detailed information please refer to the corresponding family reference manual (rm0016). 4.1 central processing unit stm8 the 8-bit stm8 core is designed for code efficiency and performance. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. architecture and registers harvard architecture 3-stage pipeline 32-bit wide program memory bus - single cycle fetching for most instructions x and y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-mbyte linear memory space 16-bit stack pointer - access to a 64 k-level stack 8-bit condition code register - 7 condition flags for the result of the last instruction addressing 20 addressing modes indexed indirect addressing mode for look-up tables located anywhere in the address space stack pointer relative addressing mode for local variables and parameter passing instruction set 80 instructions with 2-byte average instruction size standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division bit manipulation data transfer between stack and accumulator (push/pop) with direct stack access data transfer using the x and y registers or direct memory-to-memory transfers
STM8S20XXX product overview 13/81 4.2 single wire interface module (swim) and debug module (dm) the single wire interface module and debug module and permit non-intrusive, real-time in- circuit debugging and fast memory programming. swim single wire interface module for direct access to the debug module and memory programming. the interface can be activated in all device operation modes. the maximum data transmission speed is 145 bytes/ms. debug module the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, also cpu operation can be monitored in real- time by means of shadow registers. r/w to ram and peripheral registers in real-time r/w access to all resources by stalling the cpu breakpoints on all program-memory instructions (software breakpoints) 2 advanced breakpoints, 23 predefined configurations 4.3 interrupt controller nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority up to 37 external interrupts on 6 vectors including tli trap and reset interrupts 4.4 flash program and data eeprom memory up to 128 kbytes of program single voltage flash memory up to 2 k bytes true data eeprom read while write: writing in data memory possible while executing code in program memory user option byte area
product overview STM8S20XXX 14/81 write protection (wp) write protection of flash and da ta eeprom is provided to avoi d unintentional overwriting of memory that could result from a user software malfunction. there are two levels of write protection. the first level is known as mass (memory access security system). mass is always enabled and protects the main flash program memory, data eeprom and option bytes. to perform in-application programming (iap), this write protection can be removed by writing a mass key sequen ce in a control regist er. this allows the application to write to data eeprom, modify the contents of main program memory or the device option bytes. a second level of write protection, can be enabled to further protect a specific area of memory known as ubc (user boot code). refer to figure 2. the size of the ubc is programmable through the ubc option byte ( table 7. ), in increments of 1 page, by programming the ubc option byte in icp mode. this divides the program memory into two areas: main program memory: up to 128 kbytes minus ubc user-specific boot code (ubc): configurable up to 128 kbytes the ubc area remains write-protected during in-application programming. this means that the mass keys do not unlock the ubc area. it protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the iap and communication routines. figure 2. flash memory organization read-out protection (rop) the read-out protection blocks reading and writing the flash program memory and data eeprom memory in debug mode. on ce the read-out prot ection is activate d, any attempt to toggle its status triggers a global erase of the program and data memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. programmable area from i kbyte data ubc area program memory area data memory area (2 kbytes) (2 first pages) up to 128 kbytes eeprom remains write protected during iap memory 128 kbytes flash up to write access possible for iap program memory (1 page steps) option bytes
STM8S20XXX product overview 15/81 4.5 clock controller the clock controller distributes the system clock (f master ) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch-free switching. clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. master clock sources: 4 different clock sources can be used to drive the master clock: ? 1-24 mhz high speed external crystal (hse) ? up to 24 mhz high speed user-external clock (hse user-ext) ? 16 mhz high speed internal rc oscillator (hsi) ? 128 khz low speed internal rc (lsi) startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. clock security system (css): this feature can be enabled by software. if an hse clock failure occurs, the internal rc (16 mhz/ 8) is automatically selected by the css and an interrupt can optionally be generated. configurable main clock output (cco): this outputs an external clock for use by the application. 4.6 power management for efficent power management, the application can be put in one four different low-power modes. you can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. wait mode : in this mode, the cpu is stopped, but peripherals are kept running. the wake-up is performed by an internal or external interrupt or reset. fast active halt mode : in this mode, the cpu and peripheral clocks are stopped. an internal wake-up is generated at programmable intervals by the auto wake up unit (awu). the main voltage regulator is kept powered on, so current consumption is more than in slow active halt mode, but the wake-up time is faster. wake-up is triggered by the internal awu interrupt, external interrupt or reset. slow active halt mode : this mode is the same as fast active halt except that the main voltage regulator is powered off, so the wake up time is slower. halt mode : in this mode the microcontroller uses the least power, cpu and peripheral clocks are stopped, the main voltage regulator is powered off. wake-up is triggered by external interrupt or reset.
product overview STM8S20XXX 16/81 4.7 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. the wdg timer activity is controlled by option bytes. once activated the watchdog can not be disabled by the user program without reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application perfectly. the application software must refresh the counter before time-out and during a limited time window. a reset is generated in two situations: 1. timeout: at 16 mhz cpu clock the time-out period can be adjusted between 75 s up to 64 ms. 2. refresh out of window: the downcounter is refreshed before its value is lower then the one stored in the window register. independent watchdog timer the independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc cloc k source, and thus stays active even in case of a cpu clock failure the iwdg time base spans from 60 s to 1 s. 4.8 auto wake-up counter used for auto wake-up from active halt mode clock source: internal 128 khz internal low frequency rc oscillator or external clock 4.9 beeper the beeper functi on outputs a signal on the beep pin for sound gener ation. the signal is in the range of 1, 2 or 4 khz.
STM8S20XXX product overview 17/81 4.10 tim1 - 16-bit advanced control timer this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-ti me control and center-aligned pwm capability, the field of applications is extended to motor control, lighting and half-bridge driver 16-bit up, down and up/down autoreload counter with 16-bit prescaler 4 independent capture/compare channels(capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output synchronization module to control the timer with external signal break input to force the timer outputs into a defined state 3 complementary outputs with adjustable dead time encoder mode interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.11 tim2, tim3 - 16-bit general purpose timers 16-bit autoreload (ar) up-counter 15-bit prescaler adjustable to fixed power of 2 ratios 1?32768 timers with 3 or 2 individually configurable capture/compare channels pwm mode interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update 4.12 tim4 - 8-bit basic timer 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 clock source: cpu clock interrupt source: 1 x overflow/update table 3. tim timer features timer counter size (bits) prescaler counting mode capcom channels complem. outputs ext. trigger timer synchr- onization/ chaining tim1 16 any integer from 1 to 65536 up/down 4 3 yes no tim2 16 any power of 2 from 1 to 32768 up 3 0 no tim3 16 any power of 2 from 1 to 32768 up 2 0 no tim4 8 any power of 2 from 1 to 128 up 0 0 no
product overview STM8S20XXX 18/81 4.13 analog/digital converter (adc2) stm8s20x performance line products contain a 10-bit successive approximation a/d converter (adc2) with up to 16 multiplexed input channels and the following main features: ? input voltage range: 0 to v dda ? dedicated voltage reference (vref) pins available on 80 and 64-pin devices ? conversion time: 14 clock cycles ? single and continuous modes ? external trigger input ? trigger from tim1 trgo ? end of conversion (eoc) interrupt 4.14 communication interfaces the following communication interfaces are implemented: uart1: ? full feature uart, spi emulation, lin2.1 master capability, smartcard mode, irda mode, single wire mode uart3: ? full feature uart, lin2.1 master/slave capability. spi - full and half-d uplex, 10 mbit/s i2c - up to 400 kbit/s can (rev. 2.0a,b) - 3 tx mailboxes - up to 1 mbit/s 4.14.1 uart1 main features 1 mbit/s full duplex sci lin master capable spi emulation high precision baud rate generator smartcard emulation irda sir encoder decoder asynchronous communication (uart mode) full duplex communication - nrz standard format (mark/space) programmable transmit and receive baud rates up to 1 mbit/s (f cpu /16) and capable of
STM8S20XXX product overview 19/81 following any standard baud rate regardless of the input frequency separate enable bits for transmitter and receiver 2 receiver wakeup modes: ? address bit (msb) ? idle line (interrupt) transmission error detection with interrupt generation parity control lin master capability emission: generates 13-b it synch break frame reception: detects 11-bit break frame synchronous communication full duplex synchronous transfers spi master operation 8-bit data communication max. speed: 1 mbit/s at 16 mhz (f cpu /16) 4.14.2 uart3 main features 1 mbit/s full duplex sci lin master capable high precision baud rate generator asynchronous communication (uart mode) full duplex communication - nrz standard format (mark/space) programmable transmit and receive baud rates up to 1 mbit/s (f cpu /16) and capable of following any standard baud rate regardless of the input frequency separate enable bits for transmitter and receiver 2 receiver wakeup modes: ? address bit (msb) ? idle line (interrupt) transmission error detection with interrupt generation parity control lin master capability emission: generates 13-b it synch break frame reception: detects 11-bit break frame
product overview STM8S20XXX 20/81 lin slave autonomous header handling - one single interrupt per valid message header automatic baud rate synchronization - maximum tolerated initial clock deviation 15 % synch delimiter checking 11-bit lin synch break detection - break detection always active parity check on the lin identifier field lin error management hot plugging support 4.14.3 spi maximum speed: 10 mbit/s (f master /2) both for master and slave full duplex synchronous transfers simplex synchronous transfers on 2 lines with a possible bidirectional data line master or slave operation - selectable by hardware or software crc calculation 1 byte tx and rx buffer slave/master selection input pin 4.14.4 i 2 c i 2 c master features: ? clock generation ? start and stop generation i 2 c slave features: ? programmable i 2 c address detection ? stop bit detection generation and detection of 7-bit/10-bit addressing and general call supports different communication speeds: ? standard speed (up to 100 khz), ? fast speed (up to 400 khz) 4.14.5 can the becan3 controller (basic enhanced can), interfaces the can network and supports the can protocol version 2.0a and b. it has been designed to manage a high number of incoming messages efficiently with a minimum cpu load. for safety-critical applications the can controller provides all hardware functions to support the can time triggered communication option (ttcan). the maximum transmission speed is 1 mbit.
STM8S20XXX product overview 21/81 transmission ? three transmit mailboxes ? configurable transmit priority by identifier or order request ? time stamp on sof transmission reception 8-, 11- and 29-bit id 1 receive fifo (3 messages deep) software-efficient mailbox mapping at a unique address space fmi (filter match index) stored with message configurable fifo overrun time stamp on sof reception 6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking configurations, such as 12 filters for 29-bit id or 48 filters for 11-bit id filtering modes: ? mask mode permitting id range filtering ? id list mode time triggered communication option ? disable automatic retransmission mode ? 16-bit free running timer ? configurable timer resolution ? time stamp sent in last two data bytes
pinouts and pin description STM8S20XXX 22/81 5 pinouts and pin description 5.1 package pinouts figure 3. lqfp 80-pin pinout pd4 (hs)/tim2_ch1 [beep] 2 1 3 4 5 6 7 8 10 9 12 14 16 18 20 11 15 13 17 19 25 26 28 27 30 32 34 36 38 29 33 31 35 37 39 57 58 56 55 54 53 52 51 49 50 47 45 43 41 48 44 46 42 60 59 61 62 63 64 66 68 65 67 69 70 71 72 74 73 75 76 77 78 79 80 pi4 pi3 pi2 pi1 pc4 (hs)/tim1_ch4 pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pg6 pg5 pi5 pi0 pg4 pg3 pg2 pc7/spi_miso v ssio_2 v ddio_1 [tim3_ch1] tim2_ch3/pa3 uart1_rx/pa4 uart1_tx/pa5 ain12/pf4 v ssio_1 v ss vcap v dd uart1_ck/pa6 (hs) ph0 ( hs) ph1 ph2 ph3 ain15/pf7 ain14/pf6 ain13/pf5 nrst oscin/pa1 oscout/pa2 [i2c_sda] ain5/pb5 [i2c_scl] ain4/pb4 [tim1_ch2n] ain1/pb1 [tim1_ch1n] ain0/pb0 ain8/pe7 v ref- ain10/pf0 ain7/pb7 ain6/pb6 tim1_etr/ph4 tim1_ch3n/ph5 tim1_ch2n/ph6 40 ain9/pe6 21 22 24 23 ain11/pf3 v ref+ v dda v ssa pd0 (hs)/tim3_ch2 [tim1_bkin] [clk_cco] pe2/i 2c_sda pe3/tim1_bkin pe4 pg7 pd7/tli [tim1_ch4] pd6/uart3_rx pd5/uart3_tx pi7 pi6 pd2 (hs)/tim3_ch1 [tim2_ch3] pd1 (hs)/swim pc5/spi_sck pc6/spi_mosi pg0/can_tx pg1/can_rx pe0/clk_cco pd3 (hs)/tim2_ch2 [adc_etr] [tim1_etr] ain3/pb3 [tim1_ch3n] ain2/pb2 pc0/adc_etr pe5/spi_nss tim1_ch1n/ph7 v ddio_2 pe1/i2c_scl (hs) high sink capability [ ] alternate function remapping option (if the same alternat e function is shown twice, it indicates an exclusive choice not a duplication of the function).
STM8S20XXX pinouts and pin description 23/81 figure 4. lqfp 64-pin pinout v ref- ain10/pf0 ain7/pb7 ain6/pb6 [i2c_sda] ain5/pb5 [i2c_scl] ain4/pb4 [tim1_etr] ain3/pb3 [tim1_ch3n] ain2/pb2 [tim1_ch2n] ain1/pb1 [tim1_ch1n] ain0/pb0 ain8/pe7 ain9/pe6 ain11/pf3 v ref+ v dda v ssa 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ss vcap v dd v ddio_1 [tim3_ch1] tim2_ch3/pa3 uart1_rx/pa4 uart1_tx/pa5 uart1_ck/pa6 ain15/pf7 ain14/pf6 ain13/pf5 ain12/pf4 nrst oscin/pa1 oscout/pa2 v ssio_1 pg1/can_rx pg0/can_tx pc7/spi_miso pc6/spi_mosi v ddio_2 v ssio_2 pc5/spi_sck pc4 (hs)/tim1_ch4 pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pe5/spi_nss pi0 pg4 pg3 pg2 pd3 (hs)/tim2_ch2[adc_etr] pd2 (hs)/tim3_ch1[tim2_ch3] pd1 (hs)/swim pd0 (hs)/tim3_ch2 [tim1_bkin] [clk_cco] pe0/clk_cco pe1/i2c_scl pe2/i2c_sda pe3/tim1_bkin pe4 pg7 pg6 pg5 pd7/tli [tim1_ch4] pd6/uart3_rx pd5/uart3_tx pd4 (hs)/tim2_ch1 [beep] (hs) high sink capability [ ] alternate function remapping option (if the same alternat e function is shown twice, it indicates an exclusive choice not a duplication of the function).
pinouts and pin description STM8S20XXX 24/81 figure 5. lqfp 48-pin pinout 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 uart1_ck/pa6 ain8/pe7 pc1 (hs)/tim1_ch1 pe5/spi_nss pg1 ain9/pe6 pd3 (hs)/tim2_ch2 [adc_etr] pd2 (hs)/tim3_ch1 [tim2_ch3] pe0/clk_cco pe1/i2c_scl pe2/i2c_sda pe3/tim1_bkin pd7/tli [tim1_ch4] pd6/uart3_rx pd5/uart3_tx pd4 (hs)/tim2_ch1 [beep] pd1 (hs)/swim pd0 (hs)/tim3_ch2 [tim1_bkin] [clk_cco] v ssio_2 pc5/spi_sck pc4 (hs)/tim1_ch4 pc3 (hs)/tim1_ch3 p c2 (hs)/tim1_ch2 pg0 pc7/spi_miso pc6/spi_mosi v ddio_2 ain7/pb7 ain6/pb6 [i2c_sda] ain5/pb5 [i2c_scl] ain4/pb4 [tim1_etr/ain3/pb3 [tim1_ch3n] ain2/pb2 [tim1_ch2n] ain1/pb1 [tim1_ch1n] ain0/pb0 v dda v ssa v ss vcap v dd v ddio_1 [tim3_ch1] tim2_ch3/pa3 uart1_rx/pa4 uart1_tx/pa5 nrst oscin/pa1 oscout/pa2 v ssio_1 (hs) high sink capability [ ] alternate function remapping option (if the same alternat e function is shown twice, it indicates an exclusive choice not a duplication of the function).
STM8S20XXX pinouts and pin description 25/81 figure 6. lqfp 44-pin pinout ain6/pb6 [i2c_sda] ain5/pb5 [i2c_scl] ain4/pb4 [tim1_etr] ain3/pb3 [tim1_ch3n] ain2/pb2 [tim1_ch2n] ain1/pb1 (t im1_ch1n] ain0/pb0 ain9/pe6 v dda v ssa ain7/pb7 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 v ss vcap v dd v ddio_1 uart1_rx/pa4 uart1_tx/pa5 uart1_ck/pa6 nrst oscin/pa1 oscout/pa2 v ssio_1 v ddio_2 v ssio_2 pc5/spi_sck pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pe5/spi_nss pg1 pg0 pc7/spi_miso pc6/spi_mosi pd3 (hs)/tim2_ch2 [adc_etr] p d2 (hs)/tim3_ch1 [tim2_ch3] pd1 (hs)/swim pe1/i2c_scl pe2/i2c_sda pd7/tli [tim1_ch4] pd6/uart3_rx pd5/uart3_tx pd4 (hs)/tim2_ch1[beep] pe0/clk_cco pd0 (hs)/tim3_ch2 [tim1_bkin] [clk_cco] (hs) high sink capability [ ] alternate function remapping option (if the same alternat e function is shown twice, it indicates an exclusive choice not a duplication of the function).
pinouts and pin description STM8S20XXX 26/81 figure 7. vqfn32/lqfp 32-pin pinout reset state is shown in bold . table 4. legend/abbreviations type i= input, o = output, s = power supply level input cm = cmos output hs = high sink output speed o1 = slow (up to 2 mhz) o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull [i2c_scl] ain4/pb4 [tim1_etr] ain3/pb3 [tim1_ch3n] ain2/pb2 [tim1_ch2n] ain1/pb1 [tim1_ch1n] ain0/pb0 v dda v ssa [i2c_sda] ain5/pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10111213141516 1 2 3 4 5 6 7 8 vcap v dd v ddio ain12/pf4 nrst oscin/pa1 oscout/pa2 v ss pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pe5/spi_nss pc7/spi_miso pc6/spi_mosi pc5/spi_sck pc4 (hs)/tim1_ch4 pd3 (hs)/tim2_ch2 [adc_etr] pd2 (hs)/tim3_ch1[tim2_ch3] pd1 (hs)/swim pd0 (hs)/tim3_ch2 [tim1_brk] [clk_cco] pd7/tli [tim1_ch4] pd6/uart3_rx pd5/uart3_tx pd4 (hs)/tim2_ch1 [beep] (hs) high sink capability [ ] alternate function remapping option (if the same alternat e function is shown twice, it indicates an exclusive choice not a duplication of the function).
STM8S20XXX pinouts and pin description 27/81 table 5. pin description pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp44 vqfn/lqfp32 floating wpu ext. interrupt high sink speed od pp 11111nrst i/o x reset 22222pa1/oscin i/o x xo1xx port a1 resonator/ crystal in 33333pa2/oscout i/o x xx o1xx port a2 resonator/ crystal out 4444 -v ssio_1 s i/o ground 55554v ss s digital ground 6 6 6 6 5 vcap s 1.8 v regulator capacitor 77776v dd s digital power supply 88887v ddio_1 s i/o power supply 9 9 9 - - pa3/tim2_ch3 i/o x xx o1xx port a3 timer 2 - channel3 tim3_ch1 [afr1] 10 10 10 9 - pa4/uart1_rx i/o x xx o3xx port a4 uart1 receive 11 11 11 10 - pa5/uart1_tx i/o x xx o3xx port a5 uart1 transmit 12 12 12 11 - pa6/uart1_ck i/o x xx o3xx port a6 uart1 synchronous clock 13----ph0 i/o x xhso3xx port h0 14----ph1 i/o x xhso3xx port h1 15----ph2 i/o x xo1xx port h2 16----ph3 i/o x xo1xx port h3 17 13 - - - pf7/ain15 i/o x xo1xx port f7 analog input 15 18 14 - - - pf6/ain14 i/o x xo1xx port f6 analog input 14 19 15 - - - pf5/ain13 i/o x xo1xx port f5 analog input 13 20 16 - - 8 pf4/ain12 i/o x xo1xx port f4 analog input 12 21 17 - - - pf3/ain11 i/o x xo1xx port f3 analog input 11 22 18 - - - v ref+ s adc positive reference voltage 23 19 13 12 9 v dda s analog power supply
pinouts and pin description STM8S20XXX 28/81 24 20 14 13 10 v ssa s analog ground 25 21 - - - v ref- s adc negative reference voltage 26 22 - - - pf0/ain10 i/o x xo1xx port f0 analog input 10 27 23 15 14 - pb7/ain7 i/o x xx o1xx port b7 analog input 7 28 24 16 15 - pb6/ain6 i/o x xx o1xx port b6 analog input 6 29 25 17 16 11 pb5/ain5 i/o x xx o1xx port b5 analog input 5 i 2 c_sda [afr6] 30 26 18 17 12 pb4/ain4 i/o x xx o1xx port b4 analog input 4 i 2 c_scl [afr6] 31 27 19 18 13 pb3/ain3 i/o x xx o1xx port b3 analog input 3 tim1_etr [afr5] 32 28 20 19 14 pb2/ain2 i/o x xx o1xx port b2 analog input tim1_ ch3n [afr5] 33 29 21 20 15 pb1/ain1 i/o x xx o1xx port b1 analog input 1 tim1_ ch2n [afr5] 34 30 22 21 16 pb0/ain0 i/o x xx o1xx port b0 analog input 0 tim1_ ch1n [afr5] 35 - - - - ph4/tim1_etr i/o x xo1xx port h4 timer 1 - trigger input 36---- ph5/ tim1_ch3n i/o x xo1xx port h5 timer 1 - inverted channel 3 37---- ph6/ tim1_ch2n i/o x xo1xx port h6 timer 1 - inverted channel 2 38---- ph7/ tim1_ch1n i/o x xo1xx port h7 timer 1 - inverted channel 2 39 31 23 - - pe7/ain8 i/o x xx o1xx port e7 analog input 8 40 32 24 22 - pe6/ain9 i/o x xx o1xx port e7 analog input 9 41 33 25 23 17 pe5/spi_nss i/o x xx o1xx port e5 spi master/slave select table 5. pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp44 vqfn/lqfp32 floating wpu ext. interrupt high sink speed od pp
STM8S20XXX pinouts and pin description 29/81 42 - - - - pc0/adc_etr i/o x xx o1xx port c0 adc trigger input 43 34 26 24 18 pc1/tim1_ch1 i/o x xxhso3xx port c1 timer 1 - channel 1 44 35 27 25 19 pc2/tim1_ch2 i/o x xxhso3xx port c2 timer 1- channel 2 45 36 28 26 20 pc3/tim1_ch3 i/o x xxhso3xx port c3 timer 1 - channel 3 46 37 29 - 21 pc4/tim1_ch4 i/o x xxhso3xx port c4 timer 1 - channel 4 47 38 30 27 22 pc5/spi_sck i/o x xx o3xx port c5 spi clock 48 39 31 28 - v ssio_2 s i/o ground 49 40 32 29 - v ddio_2 s i/o power supply 50 41 33 30 23 pc6/spi_mosi i/o x xx o3xx port c6 spi master out/ slave in 51 42 34 31 24 pc7/spi_miso i/o x xx o3xx port c7 spi master in/ slave out 52 43 35 32 - pg0/can_tx i/o x xo1xx port g0 can transmit 53 44 36 33 - pg1/can_rx i/o x xo1xx port g1 can receive 54 45 - - - pg2 i/o x xo1xx port g2 55 46 - - - pg3 i/o x xo1xx port g3 56 47 - - - pg4 i/o x xo1xx port g4 57 48 - - - pi0 i/o x xo1xx port i0 58----pi1 i/o x xo1xx port i1 59----pi2 i/o x xo1xx port i2 60----pi3 i/o x xo1xx port i3 61----pi4 i/o x xo1xx port i4 62----pi5 i/o x xo1xx port i5 63 49 - - - pg5 i/o x xo1xx port g5 64 50 - - - pg6 i/o x xo1xx port g6 65 51 - - - pg7 i/o x xo1xx port g7 66 52 - - - pe4 i/o x xx o1xx port e4 table 5. pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp44 vqfn/lqfp32 floating wpu ext. interrupt high sink speed od pp
pinouts and pin description STM8S20XXX 30/81 5.1.1 alternate function remapping as shown in the rightmost column of the pin description table, some alternate functions can be remapped at different i/o ports by programming one of 8 afr (alternate function remap) option bits. refer to section 6: option bytes on page 31 . when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding pe ripheral must be enabled in the peripheral registers. alternate function remapping d oes not effect gpio capabilitie s of the i/o ports (see gpio section of the family reference manual, rm0016). 67 53 37 - - pe3/tim1_bkin i/o x xx o1xx port e3 timer 1 - break input 68 54 38 34 - pe2/i 2 c_sda i/o x xx o1t (1) x port e2 i 2 c data 69 55 39 35 - pe1/i 2 c_scl i/o x xx o1t (1) x port e1 i 2 c clock 70 56 40 36 - pe0/clk_cco i/o x xx o3xx port e0 configurable clock output 71----pi6 i/o x xo1xx port i6 72----pi7 i/o x xo1xx port i7 73 57 41 37 25 pd0/tim3_ch2 i/o x xxhso3xx port d0 timer 3 - channel 2 tim1_bkin [afr3]/ clk_cco [afr2] 74 58 42 38 26 pd1/swim i/o x x xhso4x x port d1 swim data interface 75 59 43 39 27 pd2/tim3_ch1 i/o x xxhso3xx port d2 timer 3 - channel 1 tim2_ch3 [afr1] 76 60 44 40 28 pd3/tim2_ch2 i/o x xxhso3xx port d3 timer 2 - channel 2 adc_etr [afr0] 77 61 45 41 29 pd4/tim2_ch1/ beep i/o x xxhso3xx port d4 timer 2 - channel 1 beep output [afr7] 78 62 46 42 30 pd5/ uart3_tx i/o x xx o1xx port d5 uart3 data transmit 79 63 47 43 31 pd6/ uart3_rx i/o x xx o1xx port d6 uart3 data receive 80 64 48 44 32 pd7/tli i/o x xx o1xx port d7 to p l ev e l interrupt tim1_ch4 [afr4] 1. in the open-drain output column, ?t? defines a true open-drain i/o (p-buffer and protection diode to v dd are not implemented) table 5. pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp44 vqfn/lqfp32 floating wpu ext. interrupt high sink speed od pp
STM8S20XXX option bytes 31/81 6 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. except for the rop (read-out protection) byte, each option byte has to be stored twice, in a regular form (optx) and a complemented one (noptx) for redundancy. option bytes can be modified in icp mode (v ia swim) by accessing the eeprom address shown in table 6: option bytes below. option bytes can also be modified ?on the fly? by the application in iap mode, except the rop and ubc options that can only be toggled in icp mode (via swim). refer to the stm8s flash programming manual (pm0051) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. table 6. option bytes addr. option name option byte no. option bits factory default setting 7654 3 2 1 0 4800h read-out protection (rop) opt0 rop[7:0] 00h 4801h user boot code(ubc) opt1 ubc[7:0] 00h 4802h nopt1 nubc[7:0] ffh 4803h alternate function remapping (afr) opt2 afr7 afr6 afr5 afr4 afr3 afr2 afr1 afr0 00h 4804h nopt2 nafr7 nafr6 nafr5 nafr4 nafr3 nafr2 nafr1 nafr0 ffh 4805h watchdog option opt3 reserved lsi _en iwdg _hw wwdg _hw wwdg _halt 00h 4806h nopt3 reserved nlsi _en niwdg_h w nwwdg _hw nwwdg_ halt ffh 4807h clock option opt4 reserved ext clk ckawu sel prs c1 prs c0 00h 4808h nopt4 reserved next clk nckawus el npr sc1 npr sc0 ffh 4809h hse clock startup opt5 hsecnt[7:0] 00h 480ah nopt5 nhsecnt[7:0] ffh 480bh reserved opt6 reserved 00h 480ch nopt6 reserved ffh 480dh flash wait states opt7 reserved wait state 00h 480eh nopt7 reserved nwait state ffh 487eh bootloader optbl bl[7:0] 00h 487fh noptbl nbl[7:0] ffh
option bytes STM8S20XXX 32/81 table 7. option byte description option byte no. description opt0 rop[7:0] memory readout protection (rop) aah: enable readout protection (w rite access via swim protocol) note: refer to the family refer ence manual (rm0016) section on flash/eeprom memory readout protection for details. opt1 ubc[7:0] user boot code area 00h: no ubc, no write-protection 01h: pages 0 to 1 defined as ubc, memory write-protected 02h: pages 0 to 3 defined as ubc, memory write-protected 03h: pages 0 to 4 defined as ubc, memory write-protected ... feh: pages 0 to 255 defined as ubc, memory write-protected ffh: reserved note: refer to the family refer ence manual (rm0016) section on flash/eeprom write protection for more details. opt2 afr7 alternate function remapping option 7 0: port d4 alternate function = tim2_ch1 1: port d4 alternate function = beep afr6 alternate function remapping option 6 0: port b5 alternate function = ai n5, port b4 alternate function = ain4 1: port b5 alternate function = i 2 c_sda, port b4 alternate function = i 2 c_scl afr5 alternate function remapping option 5 0: port b3 alternate function = ai n3, port b2 alternate function = ain2, port b1 alternate function = ain1, port b0 alternate function = ain0 1: port b3 alternate function = ti m1_etr, port b2 alternate function = tim1_ch3n, port b1 alternate functi on = tim1_ch2n, port b0 alternate function = tim1_ch1n afr4 alternate function remapping option 4 0: port d7 alternate function = tli 1: port d7 alternate function = tim1_ch4 afr3 alternate function remapping option 3 0: port d0 alternate function = tim3_ch2 1: port d0 alternate function = tim1_bkin afr2 alternate function remapping option 2 0: port d0 alternate function = tim3_ch2 1: port d0 alternate function = clk_cco note: afr2 option has priority over afr3 if both are activated afr1 alternate function remapping option 1 0: port a3 alternate function = tim2_ch3, port d2 alternate function tim3_ch1 1: port a3 alternate function = tim3_ch1, port d2 alternate function tim2_ch3 afr0 alternate function remapping option 0 0: port d3 alternate function = tim2_ch2 1: port d3 alternate function = adc_etr
STM8S20XXX option bytes 33/81 opt3 lsi_en: low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw: independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw: window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt: window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active opt4 extclk: external clock selection 0: external crystal c onnected to oscin/oscout 1: external clock signal on oscin ckawusel: auto wake-up unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler selected as clock source for for awu prsc[1:0] awu clock prescaler 00: 24 mhz to 128 khz prescaler 01: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0]: hse crystal oscillator stabilization time this configures the stabilisation time to 0, 16, 256, 4096 hse cycles. opt6 reserved opt7 waitstate wait state configuration this option configures the number of wait states inserted when reading from the flash/data eeprom memory. 1 wait state is required if f cpu > 16 mhz. 0: no wait state 1: 1 wait state optbl bl[7:0] bootloader option byte this option is checked by the boot rom code after reset. depending on content of addresses 487eh, 487fh and 8000h (reset vector) the cpu jumps to the bootloader or to the reset vector. refer to stm8s bootloader manual for more details. table 7. option byte description (continued) option byte no. description
electrical characteristics STM8S20XXX 34/81 7 electrical characteristics 7.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 7.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a = 25 c and t a = t amax (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 7.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5.0 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 7.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 7.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 8 . figure 8. pin loading conditions 50pf stm8 pin
STM8S20XXX electrical characteristics 35/81 7.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 9 . figure 9. pin input voltage 7.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in stm8 pin table 8. voltage characteristics symbol ratings min max unit v ddx - v ss supply voltage (including v dda and v ddio ) (1) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external power supply -0.3 6.5 v v in input voltage on true open drain pins (pe1, pe2) (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics STM8S20XXX 36/81 table 9. current characteristics symbol ratings max. unit i vdd total current into v dd power lines (source) (1) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external supply. 60 ma i vss total current out of v ss ground lines (sink) (1) 60 i io output current sunk by any i/o and control pin 20 output current source by any i/os and control pin - 20 i inj(pin) (2)(3) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in STM8S20XXX electrical characteristics 37/81 7.3 operating conditions table 11. general operating conditions (1) 1. tbd = to be determined. symbol parameter co nditions min max unit f cpu internal cpu clock frequency t a 105 c 0 24 mhz 0 16 mhz v dd/ v dd_io standard operating voltage 3.0 5.5 v p d power dissipation at t a = 85 c for suffix 6 or t a = 125 c for suffix 3 lqfp80 tbd mw lqfp64 tbd lqfp48 tbd lqfp44 tbd lqfp32 tbd vfqfn32 tbd t a ambient temperature for 6 suffix version maximum power dissipation -40 85 c low power dissipation (2) 2. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.4: thermal characteristics on page 67 ). -40 105 c ambient temperature for 3 suffix version maximum power dissipation -40 125 c low power dissipation (2) -40 tbd c t j junction temperature range 6 suffix version -40 105 c 3 suffix version -40 tbd c
electrical characteristics STM8S20XXX 38/81 figure 10. f cpumax versus v dd table 12. operating conditions at power-up/power-down symbol parameter conditions min typ max unit t vdd v dd rise time rate 20 (1) 1. guaranteed by design. not tested in production. s/v v dd fall time rate (2) 20 (1) t temp reset release delay v dd rising tbd (1) 3ms reset generation delay (2) 2. reset is always generated after a t temp delay. the application must ensure that v dd is still above the minimum operating voltage (v dd min) when the t temp delay has elapsed. v dd falling tbd (1) 3s v it+ power-on reset threshold 2.65 2.8 2.95 v v it- brown-out reset threshold 2.58 2.73 2.88 v v hys(bor) brown-out reset hysteresis 70 mv f cpu [mhz] supply voltage [v] 24 12 8 4 0 3.0 4.0 5.0 functionality functionality guaranteed @ t a -40 to 125 c not guaranteed in this area 16 5.5 functionality guaranteed @ t a -40 to 105 c
STM8S20XXX electrical characteristics 39/81 7.3.1 supply current characteristics the current consumption is measured as described in figure 8 on page 34 and figure 9 on page 35 . total current consumption the mcu is placed under the following conditions: all i/o pins in input mode with a static value at v dd or v ss (no load) all peripherals are disabled exce pt if explicitly mentioned. subject to general operating conditions for v dd and t a . table 13. total current consumption in run, wait and slow modes at v dd = 5.0 v (1) 1. tbd = to be determined. symbol parameter conditions typ max unit i dd(run) supply current in run mode all peripherals off, code executed from ram hse external clock/ f cpu =f master =24 mhz 5.3 tbd (2) ma hse external clock/ f cpu =f master =16 mhz 4.2 tbd ma hsi internal rc/ f cpu =f master =16 mhz 2.5 tbd ma all peripherals off, code executed from flash hse external clock/ f cpu =f master =24 mhz tbd tbd (2) ma hse external clock/ f cpu =f master =16 mhz tbd tbd ma hsi internal rc/ f cpu =f master =16 mhz tbd tbd ma i dd(wfi) supply current in wait mode cpu not clocked, all peripherals off hse external clock/ f master =24 mhz 3.3 tbd (2) 2. data based on characterization results, not tested in production ma hse external clock/ f master =16 mhz 2.9 tbd (2) ma hsi internal rc/ f master =16 mhz 1.3 tbd (2) ma i dd(slow) supply current in slow mode f cpu scaled down, all peripherals off, code executed from ram hse external clock/ f cpu =f master =16 mhz/128 2.7 tbd (2) ma hsi internal rc/ f cpu =f master =16 mhz/128 1.0 tbd (2) ma
electrical characteristics STM8S20XXX 40/81 table 14. total current consumption and timing in halt, fast active halt and slow active halt modes at v dd = 5.0 v (1) 1. tbd = to be determined. symbol parameter conditions typ max unit i dd(h) supply current in halt mode 5.5 tbd a i dd(fah) supply current in fast active halt mode hse osc 16 mhz 600 tbd (2) 2. data based on characterization results, not tested in production lsi rc 128 khz 250 tbd (2) i dd(sah) supply current in slow active halt mode hse osc 16 mhz 490 tbd (2) lsi rc 128 khz 11.5 tbd (2) t wu(fah) wake-up time from fast active halt mode to run mode 2 (2) s t wu(sah) wake-up time from slow active halt mode to run mode 100 (2) s table 15. total current consumption in run, wait and slow modes at v dd = 3.3 v (1) 1. tbd = to be determined. symbol parameter conditions typ max (2) 2. data based on characterisation results, not tested in production unit i dd(run) supply current in run mode all peripherals off, code executed from ram hse external clock/ f cpu =f master =24 mhz 4.7 tbd ma hse external clock/ f cpu =f master =16 mhz 3.6 tbd ma hsi internal rc/ f cpu =f master =16 mhz 2.6 tbd ma i dd(wfi) supply current in wait mode cpu not clocked, all peripherals off hse external clock/ f master =24 mhz 2.7 tbd ma hse external clock/ f master =16 mhz 2.3 tbd ma hsi internal rc/ f master =16 mhz 1.3 tbd ma i dd(slow) supply current in slow mode f cpu scaled down, all peripherals off, code executed from ram hse external clock/ f cpu =f master =16 mhz/128 2.1 tbd ma hsi internal rc/ f cpu =f master =16 mhz/128 1.1 tbd ma
STM8S20XXX electrical characteristics 41/81 table 16. total current consumption and timing in halt, fast active halt and slow active halt modes at v dd = 3.3 v (1) 1. tbd = to be determined. symbol parameter conditions typ max (2) 2. data based on characterization results, not tested in production unit i dd(h) supply current in halt mode all clocks off 4.0 tbd a i dd(fah) supply current in fast active halt mode auto wake-up unit (awu) active hse osc 16 mhz 560 tbd lsi rc 128 khz 145 tbd i dd(sah) supply current in slow active halt mode hse osc 16 mhz 430 tbd lsi rc 128 khz 9.5 tbd t wu(fah) wake-up time from fast active halt mode to run mode 2s t wu(sah) wake-up time from slow active halt mode to run mode 100 s
electrical characteristics STM8S20XXX 42/81 on-chip peripherals table 17. peripheral current consumption (1) 1. tbd = to be determined. symbol parameter typ. v dd = 3.3 v typ. v dd = 5 v unit i dd(tim1) tim1 supply current (2) 2. data based on a differential i dd measurement between reset configur ation and timer counter running at 16 mhz. no ic/oc programmed (no i/o pads toggling). not tested in production. tbd tbd ma i dd(tim2) tim2 supply current (2) tbd tbd i dd(tim3) tim3 timer supply current (2) tbd tbd i dd(tim4) tim4 timer supply current (2) tbd tbd i dd(uart1) uart1 supply current (3) 3. data based on a differential i dd measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocke d and not kept under reset. no i/o pads toggling. tbd tbd i dd(uart3) uart3 supply current (3) tbd tbd i dd(spi) spi supply current (3) tbd tbd i dd(i 2 c) i 2 c supply current (3) tbd tbd i dd(can) can supply current (4) 4. data based on a differential idd measurement between reset configuration (can disabled) and a permanent can data transmit sequence in loopback m ode at 1mhz. this measurement does not include the pad toggling consumption. tbd tbd i dd(adc2) adc2 supply current when converting (5) 5. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. tbd tbd
STM8S20XXX electrical characteristics 43/81 current consumption curves figure 11 to figure 16 show typical current consumption measured with code executing in ram. figure 11. typ. i dd(run)hse vs. v dd @f cpu =16mhz figure 12. typ. i dd(run)hse vs. f cpu @v dd =5.0v 0 1 2 3 4 5 6 7 8 9 10 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] i dd(run)hse [ma] -40c 25c 85c 125c 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 fcpu [mhz] i dd(run)hse [ma] -40c 25c 85c 125c figure 13. typ. i dd(run)hsi vs. v dd @f cpu =16mhz figure 14. typ. i dd(wfi)hse vs. v dd @f cpu =16mhz 0 0.5 1 1.5 2 2.5 3 3.5 4 2.533.54 4.555.56 v dd [v] i dd(run)hsi [ma] -40c 25c 85c 125c 0 1 2 3 4 5 6 2.533.544.555.56 v dd [v] i dd(wfi)hs e [ma] -40c 25c 85c 125c figure 15. typ. i dd(wfi)hse vs. f cpu @v dd =5.0v figure 16. typ. i dd(wfi)hsi vs. v dd @f cpu =16mhz 0 1 2 3 4 5 6 0 5 10 15 20 25 30 fcpu [mhz] i dd(wfi)hse [ma] -40c 25c 85c 125c 0 0.5 1 1.5 2 2.5 2.533.54 4.555.56 v dd [v] i dd(w fi)hsi [ma] -40c 25c 85c 125c
electrical characteristics STM8S20XXX 44/81 7.3.2 external clock sources and timing characteristics hse user external clock subject to general operating conditions for v dd and t a . figure 17. hse external clock source table 18. hse user external clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency 024mhz v hseh oscin input pin high level voltage 0.7 x v dd v dd v v hsel oscin input pin low level voltage v ss 0.3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd -1 +1 a oscin f hse external clock stm8 source v hsel v hseh
STM8S20XXX electrical characteristics 45/81 hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 24 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization result s with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to the crys tal resonator manufactur er for more details (frequency, package, accuracy...). figure 18. hse oscillator circuit diagram hse oscillator critical g m formula r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (s ee crystal specification) co: shunt capacitance (see crystal specification) c l1 =c l2 =c: grounded external capacitance g m >> g mcrit table 19. hse oscillator characteristics symbol parameter conditions min typ max unit r f feedback resistor 220 k c (1) recommended load capacitance (2) 20 pf i dd(hse) hse oscillator power consumption c = 20 pf 6 (startup) 2 (stabilized) ma c = 10 pf 6 (startup) 1.5 (stabilized) g m oscillator transconductance 5 ma/v t su(hse) (3) startup time v dd is stabilized 1ms 1. c is approximately equivalent to 2 x crystal cload. 2. the oscillator selection can be optimized in terms of supply current using a high qual ity resonator with small r m value. refer to crystal manufacturer for more details 3. t su(hse) is the start-up time measured from the moment it is enabled (by software) to a stabi lized 24 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. oscout oscin f hse to core c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator g mcrit 2 hse f () 2 r m 2co c + () 2 =
electrical characteristics STM8S20XXX 46/81 7.3.3 internal clock sources and timing characteristics subject to general operating conditions for v dd and t a . high speed internal rc oscillator (hsi) figure 19. typical hsi frequency vs v dd @ 4 temperatures table 20. hsi oscillator characteristics (1) 1. tbd = to be determined. symbol parameter conditions min typ max unit f hsi frequency 16 mhz acc hsi accuracy of hsi oscillator tr i m m e d b y t h e application for given v dd and t a conditions -1 (2) 2. guaranteeed by design. not tested in production. 1 (2) % accuracy of hsi oscillator (factory calibrated) v dd = 5.0 v, t a = 25c -2 2 % v dd = 5.0 v, 25 c t a 85 c tbd tbd % v dd = 5.0 v, 25 c t a 125 c tbd tbd % v dd = 3.0 v v dd 5.5 v, -40 c t a 125 c tbd (3) 3. data based on characterization results, not tested in production tbd (3) % t su(hsi) hsi oscillator wake-up time including calibration 1 tbd (3) s i dd(hsi) hsi oscillator power consumption 170 250 (3) a -3% -2% -1% 0% 1% 2% 3% 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] hsi frequency variation [%] -40c 25c 85c 125c
STM8S20XXX electrical characteristics 47/81 low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . figure 20. typical lsi frequency vs v dd @ 4 temperatures table 21. lsi oscillator characteristics (1) 1. tbd = to be determined. symbol parameter conditions min typ max unit f lsi frequency tbd 128 tbd khz t su(lsi) lsi oscillator wake-up time 7 tbd (2) 2. data based on characterization results, not tested in production. s i dd(lsi) lsi oscillator power consumption 5 tbd (2) a -3% -2% -1% 0% 1% 2% 3% 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] lsi frequency variation [%] -40c 25c 85c 125c
electrical characteristics STM8S20XXX 48/81 7.3.4 memory characteristics ram and hardware registers flash program memory/data eeprom memory general conditions: t a = -40 to 125 c. table 22. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by design, not tested in production. refer to table 12 on page 38 for the value of v it-max halt mode (or reset) v it-max v table 23. flash program memory/data eeprom memory (1) 1. tbd = to be determined. symbol parameter conditions min (2) 2. guaranteed by characterizati on, not tested in production. typ max unit v dd operating voltage (all modes, execution/write/erase) f cpu 24 mhz 3.0 5.5 v t prog standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) 66.6ms fast programming time for 1 block (128 bytes) 33.3ms t erase erase time for 1 block (128 bytes) 3 3.3 ms n rw erase/write cycles (3) (program memory) 3. the physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. t a = +85 c 10k cycles erase/write cycles (data memory) (3) t a = +125 c 300k 1m t ret data retention (program memory) after 10k erase/write cycles at t a = +55 c t ret =55c 20 years data retention (data memory) after 300k erase/write cycles at t a = +125 c t ret =85c 1 i dd supply current (flash programming or erasing for 1 to 128 bytes) v dd = 3.3 v tbd tbd ma v dd = 5.0 v tbd tbd
STM8S20XXX electrical characteristics 49/81 7.3.5 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 24. i/o static characteristics (1) symbol parameter conditions min typ max unit v il input low level voltage v dd = 5.0 v -0.3 v tbd v v ih input high level voltage 0.7 x v dd v dd + 0.3 v v v hys hysteresis (2) 700 mv r pu pull-up resistor v dd = 5 v, v in =v ss 30 45 60 k t r , t f rise and fall time (10% - 90%) fast i/os load = 50 pf 20 (3) ns standard and high sink i/os load = 50 pf 125 (3) ns i lkg input leakage current, analog and digital v ss v in v dd 1 (3) a i lkg ana analog input leakage current v ss v in v dd 250 (3) na i lkg(inj) leakage current in adjacent i/o (3) injection current 4 ma 1 (3) a 1. tbd = to be determined. 2. hysteresis voltage between schmitt trigger switching levels . based on characterization results, not tested in production. 3. data based on characterization results, not tested in production.
electrical characteristics STM8S20XXX 50/81 figure 21. typical v il and v ih vs v dd @ 4 temperatures figure 22. typical pull-up resistance r pu vs v dd @ 4 temperatures figure 23. typical pull-up current i pu vs v dd @ 4 temperatures 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] v il / v ih [v] -40c 25c 85c 125c 30 35 40 45 50 55 60 2.53 3.544.55 5.56 v dd [v] pull-up resistance [k ohm ] -40c 25c 85c 125c 0 20 40 60 80 100 120 140 0123456 v dd [v] pull-up current [a] -40c 25c 85c 125c note: the pull-up is a pure resistor (slope goes through 0).
STM8S20XXX electrical characteristics 51/81 table 25. output driving current (standard ports) symbol parameter conditions min max unit v ol output low level with 4 pins sunk i io = 4 ma,v dd = 3.3 v 1000 (1) mv output low level with 8 pins sunk i io = 10 ma,v dd = 5.0 v 2000 v oh output high level with 4 pins sourced i io = 4 ma, v dd = 3.3 v 2.1 (1) v output high level with 8 pins sourced i io = 10 ma, v dd = 5.0 v 2.8 1. data based on characterization results, not tested in production table 26. output driving current (true open drain ports) symbol parameter conditions min max unit v ol output low level with 2 pins sunk i io = 10 ma, v dd = 3.3 v 1500 (1) mv i io = 10 ma, v dd = 5.0 v 1000 i io = 20 ma, v dd = 5.0 v tbd (1) 1. data based on characterization results, not tested in production table 27. output driving current (high sink ports) symbol parameter conditions min max unit v ol output low level with 4 pins sunk i io = 10 ma,v dd = 3.3 v 1000 (1) mv output low level with 8 pins sunk i io = 10 ma,v dd = 5.0 v 800 output low level with 4 pins sunk i io = 20 ma,v dd = 5.0 v 1500 (1) v oh output high level with 4 pins sourced i io = 10 ma, v dd = 3.3 v 2.1 (1) v output high level with 8 pins sourced i io = 10 ma, v dd = 5.0 v 4.0 output high level with 4 pins sourced i io = 20 ma, v dd = 5.0 v 3.3 (1) 1. data based on characterization results, not tested in production
electrical characteristics STM8S20XXX 52/81 typical output level curves figure 24 to figure 33 show typical output level curves measured with output on a single pin. figure 24. typ. v ol @ v dd = 3.3 v (standard ports) figure 25. typ. v ol @ v dd = 5.0 v (standard ports) 0 0.25 0.5 0.75 1 1.25 1.5 01234567 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 024681012 i ol [ma] v ol [v] -40c 25c 85c 125c figure 26. typ. v ol @ v dd = 3.3 v (true open drain ports) figure 27. typ. v ol @ v dd = 5.0 v (true open drain ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c figure 28. typ. v ol @ v dd = 3.3 v (high sink ports) figure 29. typ. v ol @ v dd = 5.0 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 02468101214 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c
STM8S20XXX electrical characteristics 53/81 figure 30. typ. v dd - v oh @ v dd = 3.3 v (standard ports) figure 31. typ. v dd - v oh @ v dd = 5.0 v (standard ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 01234567 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 024681012 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c figure 32. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) figure 33. typ. v dd - v oh @ v dd = 5.0 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c
electrical characteristics STM8S20XXX 54/81 7.3.6 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. figure 34. typical nrst v il and v ih vs v dd @ 4 temperatures table 28. nrst pin characteristics (1) 1. tbd = to be determined. symbol parameter conditions min typ 1) max unit v il(nrst) nrst input low level voltage (2) 2. data based on characterization results, not tested in production. v ss tbd v v ih(nrst) nrst input high level voltage (2) tbd v dd v ol(nrst) nrst output low level voltage (2) i ol =tbd ma tbd r pu(nrst) nrst pull-up resistor (3) 3. the r pu pull-up equivalent resistor is based on a resistive transistor 30 40 60 k v f(nrst) nrst input filtered pulse (4) 4. data guaranteed by design, not tested in production. tbd ns v nf(nrst) nrst input not filtered pulse (4) tbd s 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] v il / v ih [v] -40c 25c 85c 125c
STM8S20XXX electrical characteristics 55/81 figure 35. typical nrst pull-up resistance r pu vs v dd @ 4 temperatures figure 36. typical nrst pull-up current i pu vs v dd @ 4 temperatures the reset network shown in figure 37 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il max. level specified in ta bl e 2 4 . otherwise the reset is not taken into account internally. figure 37. recommended reset pin protection 30 35 40 45 50 55 60 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] nrst pull-up resistance [k ohm ] -40c 25c 85c 125c 0 20 40 60 80 100 120 140 0123456 v dd [v] nrst pull-up current [a] -40c 25c 85c 125c 0.01f external reset circuit stm8 filter r pu v dd internal reset nrst
electrical characteristics STM8S20XXX 56/81 7.3.7 tim timer characteristics subject to general operating conditions for v dd , f master , and t a unless otherwise specified. table 29. tim 1, 2, 3 characteristics symbol parameter conditions min typ max unit t w(icap)in input capture pulse time (1) 1. guaranteed by design. 2t master t res(tim) timer resolution time (1) 1t master f ext timer external clock frequency (1) 24 mhz res tim timer resolution (1) 16 bit t counter 16-bit counter clock period when internal clock is selected (1) 1t master t max_count maximum possible count (1) 65,536 t master
STM8S20XXX electrical characteristics 57/81 7.3.8 spi serial peripheral interface unless otherwise specified, the parameters given in ta bl e 3 0 are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss , sck, mosi, miso). table 30. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 0 10 mhz slave mode 0 10 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 25 ns t su(nss) (1) nss setup time slave mode 4*t master t h(nss) (1) nss hold time slave mode 70 t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f master = 16 mhz, f sck = 8 mhz 110 140 t su(mi) (1) t su(si) (1) data input setup time master mode 5 slave mode 2 t h(mi) (1) t h(si) (1) data input hold time master mode, f master = 16 mhz, f sck = 8 mhz 7 slave mode, f master = 16 mhz, f sck = 8 mhz 3 t a(so) (1)(2) data output access time slave mode, f master = 16 mhz, f sck = 8 mhz 400 slave mode 4*t master t dis(so) (1)(3) data output disable time slave mode 25 t v(so) (1) data output valid time slave mode (after enable edge), f master = 16 mhz, f sck = 8 mhz 100 t v(mo) (1) data output valid time master mode (after enable edge), f master = 16 mhz, f sck = 8 mhz 3 t h(so) (1) data output hold time slave mode (after enable edge) 100 t h(mo) (1) master mode (after enable edge) 6 1. values based on design simulation and/or charac terization results, and not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z.
electrical characteristics STM8S20XXX 58/81 figure 38. spi timing diagram - slave mode and cpha=0 figure 39. spi timing diagram - slave mode and cpha=1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134 sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
STM8S20XXX electrical characteristics 59/81 figure 40. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
electrical characteristics STM8S20XXX 60/81 7.3.9 i2c interface characteristics table 31. i 2 c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) 1. f master , must be at least 8 mhz to achieve max fast i 2 c speed (400khz) unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production max (2) min (2) max (2) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low time 0 (4) 4. the device must internally provide a hold time of at least 300 ns for th e sda signal in order to bridge the undefined region of the falling edge of scl 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf
STM8S20XXX electrical characteristics 61/81 7.3.10 10-bit adc characteristics subject to general operating conditions for v dda , f master , and t a unless otherwise specified. table 32. adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency v dda = 3 to 5.5 v 14 mhz v dda = 4.5 to 5.5 v 16 v dda analog supply 3 5.5 v v ref+ positive reference voltage 2.75 v dda v v ref- negative reference voltage v ssa 0.5 v v ain conversion voltage range (1) 1. during the sample time the input capacitance c ain (3 pf max) can be char ged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming. v ssa v dda v devices with external v ref+ / v ref- pins v ref- v ref+ v c adc internal sample and hold capacitor 3pf t s (1) minimum sampling time f adc = 4 mhz 0.75 s f adc = 6 mhz 0.5 t stab wake-up time from standby 7 s t conv minimum total conversion time (including sampling time, 10-bit resolution) f adc = 4 mhz 3.5 s f adc = 6 mhz 2.33 s 14 1/f adc
electrical characteristics STM8S20XXX 62/81 table 33. adc accuracy with r ain < 10 k r ain , v dda = 3.3 v (1) 1. tbd = to be determined. symbol parameter conditions typ max unit |e t | total unadjusted error (2) f adc = 3 mhz. 1.5 tbd lsb f adc = 4 mhz. 2.2 tbd |e o | offset error (2) f adc = 3 mhz. 1.1 tbd f adc = 4 mhz. 1.4 tbd |e g | gain error (2) f adc = 3 mhz. -0.2/0.6 tbd f adc = 4 mhz. -0.1/1.1 tbd |e d | differential linearity error (2) f adc = 3 mhz. 0.9 tbd f adc = 4 mhz. 0.9 tbd |e l | integral linearity error (2) f adc = 3 mhz. 1tbd f adc = 4 mhz. 1tbd table 34. adc accuracy with r ain < 10 k , v dda = 5 v (1) 1. tbd = to be determined. symbol parameter conditions typ max unit |e t | total unadjusted error (2) 2. adc accuracy vs. negative injection current: injecti ng negative current on any of the analog input pins should be avoided as this significant ly reduces the accuracy of the conversion being per formed on another analog input. it is recommended to add a schottky diode (p in to ground) to standard analog pins which may potentially inject negative current. any positive inje ction current within the limits specified for i inj(pin) and i inj(pin) in section 7.3.5 does not affect the adc accuracy. f adc = 2 mhz. 1tbd lsb f adc = 4 mhz. 1.7 tbd f adc = 6 mhz. 2.2 tbd |e o | offset error (2) f adc = 2 mhz. 0.7 tbd f adc = 4 mhz. 1tbd f adc = 6 mhz. 1.8 tbd |e g | gain error (2) f adc = 2 mhz. -0.03 tbd f adc = 4 mhz. 0.6 tbd f adc = 6 mhz. 1.3 tbd |e d | differential linearity error (2) f adc = 2 mhz. 0.8 tbd f adc = 4 mhz. 0.9 tbd f adc = 6 mhz. 0.9 tbd |e l | integral linearity error (2) f adc = 2 mhz. 0.6 tbd f adc = 4 mhz. 0.8 tbd f adc = 6 mhz. 0.8 tbd
STM8S20XXX electrical characteristics 63/81 figure 41. adc accura cy characteristics 1. example of an actual transfer curve. 2. the ideal transfer curve 3. end point correlation line e t = total unadjusted error: maximum deviation betw een the actual and the ideal transfer curves. e o = offset error: deviation between the firs t actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum dev iation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition an d the end point correlation line. figure 42. typical application with adc e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021102210231024 (1) (2) e t e d e l (3) v dda v ssa ainx stm8 v dd i l 1a v t 0.6v v t 0.6v c adc v ain r ain 10-bit a/d conversion c ain
electrical characteristics STM8S20XXX 64/81 7.3.11 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. functional ems (electromagnetic susceptibility) while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application.
STM8S20XXX electrical characteristics 65/81 software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nr st pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) emission tests conform to the sae j 1752/3 standard for test software, board layout and pin loading. absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. table 35. ems data symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f master = 16 mhz (hsi clock), conforms to iec 1000-4-2 3b v eftb fast transient voltage burst limits to be applied through 100pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f master = 16 mhz (hsi clock) conforms to iec 1000-4-4 4a table 36. emi data symbol parameter conditions unit general conditions monitored frequency band max f cpu (1) 8 mhz 16 mhz 24 mhz s emi peak level v dd = 5 v, t a = +25 c, lqfp80 package conforming to sae j 1752/3 0.1mhz to 30 mhz 15 17 22 dbv 30 mhz to 130 mhz 18 22 16 130 mhz to 1 ghz -1 3 5 sae emi level 2 2.5 2.5 - 1. data based on characterization results, not tested in production.
electrical characteristics STM8S20XXX 66/81 electrostatic discharge (esd) electrostatic discharges (3 positive then 3 n egative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. for more details, refer to the application note an1181. static latch-up two complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. table 37. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25c, conforming to jesd22-a114 a2000v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25c, conforming to jesd22-c101 iv 1000 v table 38. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). lu static latch-up class t a = +25 c a t a = +85 c a t a = +125 c a
STM8S20XXX electrical characteristics 67/81 7.4 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in table 11: general operating conditions on page 37 . the maximum chip-junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: t amax is the maximum ambient temperature in c ja is the package junction-to-ambient thermal resistance in c/w p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh )*i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. 7.4.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 39. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient lqfp 80 - 14 x 14 mm 38 c/w ja thermal resistance junction-ambient lqfp 64 - 10 x 10 mm 46 c/w ja thermal resistance junction-ambient lqfp 48 - 7 x 7 mm 57 c/w ja thermal resistance junction-ambient lqfp 44 - 10 x 10 mm 54 c/w ja thermal resistance junction-ambient lqfp 32 - 7 x 7 mm 59 c/w ja thermal resistance junction-ambient vfqfn 32 - 5 x 5 mm 21.6 c/w
electrical characteristics STM8S20XXX 68/81 7.4.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the order code (see figure 50: stm8s207/208xx performance line ordering information scheme on page 79 ). the following example shows how to calculate the temperature range needed for a given application. assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 8 ma, v dd = 5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 8 ma x 5 v= 400 mw p iomax = 20 x 8 ma x 0.4 v = 64 mw this gives: p intmax = 400 mw and p iomax 64 mw: p dmax = 400 mw + 64 mw thus: p dmax = 464 mw using the values obtained in table 39: thermal characteristics on page 67 t jmax is calculated as follows: ? for lqfp64 46c/w t jmax = 82 c + (46 c/w x 464 mw) = 82c + 21c = 103 c this is within the range of the suffix 6 version parts (-40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6.
STM8S20XXX package characteristics 69/81 8 package characteristics in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack ? specifications are available at www.st.com .
package characteristics STM8S20XXX 70/81 8.1 package mechanical data 8.1.1 lqfp package mechanical data figure 43. 80-pin low profile quad flat package (14 x 14) table 40. 80-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.22 0.32 0.38 0.0087 0.0126 0.0150 c 0.09 0.20 0.0035 0.0079 d 16.00 0.6299 d1 14.00 0.5512 e 16.00 0.6299 e1 14.00 0.5512 e 0.65 0.0256 q 03.57 03.57 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 a a2 a1 b e h c l l1 e e1 d1 d
STM8S20XXX package characteristics 71/81 figure 44. 64-pin low profile quad flat package (10 x 10) table 41. 64-pin low profile quad flat package mechanical data (10 x 10) dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 k 03.57 03.57 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 l1 l k 0.10mm .004 seating plane a a2 a1 b e c d d1 d3 e e1 e3 pin 1 identification m x 45
package characteristics STM8S20XXX 72/81 figure 45. 64-pin low profile quad flat package (14 x14) table 42. 64-pin low profile quad flat package mechanical data (14 x14) dim. mm inches (1) 1. values in inches are converted from mm and rounded to 3 decimal digits min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.80 0.031 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n64 c h l l1 e b a a1 a2 e e1 d d1
STM8S20XXX package characteristics 73/81 figure 46. 48-pin low profile quad flat package (7 x 7) table 43. 48-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 9.00 0.3543 d1 7.00 0.2756 e 9.00 0.3543 e1 7.00 0.2756 e 0.50 0.0197 q 03.57 03.57 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 e e1 d d1 l1 l c e b a1 a2 a
package characteristics STM8S20XXX 74/81 figure 47. 44-pin low profile quad flat package (10 x 10) table 44. 44-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.80 0.0315 q 03.57 03.57 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 a a2 a1 b e l1 l h c e e1 d d1
STM8S20XXX package characteristics 75/81 figure 48. 32-pin low profile quad flat package (7 x 7) table 45. 32-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 9.00 0.3543 d1 7.00 0.2756 e 9.00 0.3543 e1 7.00 0.2756 e 0.80 0.0315 q 03.57 03.57 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 h c l l1 b e a1 a2 a e e1 d d1
package characteristics STM8S20XXX 76/81 8.1.2 qfn package mechanical data figure 49. 32-lead very thin fine pitch quad flat no-lead package (5 x 5) 1. tbd = to be determined. table 46. 32-lead very thin fine pitch quad flat no-lead package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0 0.02 0.05 0.0008 0.0020 a3 0.20 0.0079 b 0.18 0.25 0.30 0.0071 0.0098 0.0118 d 4.85 5.00 5.15 0.1909 0.1969 0.2028 d2 3.20 3.45 3.70 0.1260 0.1457 e 4.85 5.00 5.15 0.1909 0.1969 0.2028 e2 3.20 3.45 3.70 0.1260 0.1358 0.1457 e 0.50 0.0197 l 0.30 0.40 0.50 0.0118 0.0157 0.0197 ddd 0.08 0.0031 seating plane ddd c c a3 a1 a d e 9 16 17 24 32 pin # 1 id r = 0.30 8 e l l d2 1 b e2 42_me bottom view
STM8S20XXX stm8 development tools 77/81 9 stm8 development tools development tools for the stm8 microcontrollers include the full-featured stice emulation system supported by a complete software tool package including c compiler, assembler and integrated development environment with high-level language debugger. in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 9.1 emulation and in-circuit debugging tools the stm8 tool line includes the full-featured stice emulation system offering a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. in addition , stm8 application development is supported by a low-cost in-circu it debugger/programmer. the stice is the fourth generation of full featured emulators from stmicroelectronics. it offers new advanced debugging capabilities incl uding profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addition, stice offers in-circuit debugging and programming of stm8 microcontrollers via the stm8 single wire interface module (swim), which allows non- intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. stice key features occurrence and time profiling and code coverage (new features) advanced breakpoints with up to 4 levels of conditions data breakpoints program and data trace recording up to 128 k records read/write on the fly of memory during emulation in-circuit debugging/programming via swim protocol 8-bit probe analyzer 1 input and 2 output triggers power supply follower managing application voltages between 1.62 to 5.5 v modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8
stm8 development tools STM8S20XXX 78/81 9.2 software tools stm8 development tools are supported by a complete, free software package from stmi- croelectronics that includes st visual develop (stvd) ide and the st visual programmer (stvp) software interface. stvd provides seam less integration of the cosmic c compiler for stm8, which is available in a free version that outputs up to 16 kbytes of code. 9.2.1 stm8 toolset stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com/mcu. this package includes: st visual develop ? full-featured integrated development environment from st, featuring seamless integration of c and asm toolsets full-featured debugger project management syntax highlighting editor integrated programming interface support of advanced emulation features fo r stice such as code profiling and coverage st visual programmer (stvp) ? easy-to-use, unlimited graphic al interface allowing read, write and verify of your stm8 microcontroller?s flash memory. stvp also offers project mode for saving programming configurations and automating programming sequences. 9.2.2 c and assembly toolchains control of c and assembly toolchains is seam lessly integrated into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. available toolchains include: cosmic c compiler for stm8 ? available in a free version that outputs up to 16 kbytes of code. for more information, see www.cosmic-software.com. raisonance c compiler for stm8 ? available in a free version that outputs up to 16 kbytes of code. for more information, see www.raisonance.com. st7/stm8 assembler linker ? free assembly toolchain included in the stvd toolset, which allows you to assemble and link your application source code. 9.3 programming tools during the development cycle, stice provides in-circuit programming of the stm8 flash microcontroller on your application board via the swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming your stm8. for production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the stm8 family.
STM8S20XXX ordering information 79/81 10 ordering information figure 50. stm8s207/208xx performance line ordering information scheme stm8 s 208 m b t 6 b product class stm8 microcontroller pin count k = 32 pins s = 44 pins c = 48 pins r = 64 pins m = 80 pins package type t = lqfp u = vfqfpn example: sub-family type 208 = full peripheral set 207 = intermediate peripheral set family type s = standard temperature range 3 = -40 c to 125 c 6 = -40 c to 85 c for a list of available options (e.g. memory size, package) and order able part numbers or for further information on any aspect of this device, please go to www .st.com or contact the st sales office nearest to you. program memory size 4 = 16k 6 = 32k 8 = 64k b = 128k package pitch no character = 0.5 mm b = 0.65 mm c = 0.8 mm packing no character = tray or tube tr = tape and reel
revision history STM8S20XXX 80/81 11 revision history table 47. document revision history date revision changes 23-may-2008 1 initial release. 05-jun-2008 2 added part numbers on page 1 and in table 2 on page 10 . updated section 4: product overview updated section 7: electrical characteristics 22-jun-2008 3 added part numbers on page 1 and in table 2 on page 10 . 12-aug-2008 4 added 32 pin device pinout and ordering information. updated ubc option description in table 7 on page 32 usart renamed uart1, linuart renamed uart3. max. adc frequency increased to 6 mhz.
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